This invention relates generally to logic circuits and more particularly to testable logic circuits.
Modern digital electronics continue to become more and more complex. This increased complexity places greater and greater demands on the underlying semiconductor technology to allow these designs to be integrated into a single integrated circuit. The advantages of integrated circuits are well known: faster speeds, lower manufacturing costs and higher reliability.
One approach to improving the speed and reducing the transistor count, and hence the die size in existing designs, is to use dynamic logic in place of static logic. There are several dynamic logic families: Domino CMOS and differential cascode voltage swing logic (DCVS) and their derivatives, which include no race logic (NORA), N-P Domino or Zipper CMOS, latch Domino, cascode voltage switch logic (CVSL), sample set differential logic (SSDL), and clocked CMOS logic. The DCVS logic implements both true and complementary functions using nMOS transistors. As a result, the transistor count in DCVS logic is generally high and therefore significant area savings over static CMOS is generally not achieved. Domino CMOS logic, on the other hand, uses a pseudo nMOS structure that does yield a significant reduction in transistor count over static CMOS. In addition, Domino logic has a smaller pull-up delay and negligible short-circuit current resulting from the dynamic operation. Therefore, Domino CMOS logic appears to be a potentially viable logic family for the levels of integration forecasted for future generations of ICs.
The main difficulty in adopting the Domino logic family is testing. Several references have discussed testing Domino CMOS logic. See, e.g., R. Rajsuman, "Digital Hardware Testing", pp. 38-42, 1992; V. G. Oklobdzija and P. G. Kovijanic, "On Testability of CMOS-Domino Logic", Proc. FTCS, pp. 50-55, 1984; and N. K. Jha, "Testing for Multiple Faults in Domino-CMOS Logic Circuits", IEEE Trans. CAD, Vol. 7, pp. 109-116, Jan. 1988. All of these references, however, make the operating assumption that the Domino CMOS logic circuit is comprised of purely combinational Domino gates. Sequential Domino logic was considered too complex and as a result has not been addressed. In reality, this assumption is not valid because pure combinational Domino logic has very limited use. Currently, as well as for the foreseeable future, most designs are done in static CMOS logic. There are several reasons for this. First, most CAD design tools do not support Domino logic and, therefore, any synthesis tools generate only static logic designs. Second, most circuit designers do not work from scratch. They take existing designs, which are almost exclusively in static CMOS, and integrate those into a new design so as to leverage the design and testing work that was done on those existing blocks. If Domino CMOS logic is to be used, at least for the foreseeable future, it will be in combination with static CMOS logic. The problem is that there is no existing technique to test these "hybrid" circuits that include both static CMOS and dynamic Domino CMOS logic.
The difficulty of testing Domino CMOS gates is apparent upon examining the general structure of a Domino CMOS gate. Such a gate is shown generally at 10 in FIG. 1A. The generic logic gate 10 includes an nMOS block 12, which implements the logic function, a pMOS transistor 14, an nMOS transistor 16, and a load inverter 18. A clock signal is applied to the gates of transistors 14 and 16 at input terminal 20 and one or more input signals are provided to the nMOS block 12 on inputs 22. An output signal is provided on an output 24 coupled to the output terminal of the load inverter 18. An alternative embodiment of gate 10 is shown in FIG. 1B, which includes an additional pMOS transistor 26 to maintain the voltage level at intermediate node W at the input of the load inverter 18. The gate of pMOS transistor 26 can either be coupled to ground thereby turning the transistor permanently on or, alternatively, connected to the output node 24 so that the transistor 26 is only turned on when the output is 0.
The operation of Domino CMOS logic takes place in two distinct phases: a precharge phase and an evaluation phase. The precharge phase occurs when the clock signal is 0. In this phase, transistor 14 is turned on and transistor 16 is turned off. In both structures of FIG. 1, the node W is precharged to 1 during the precharge phase. Thus, when the clock signal is 0, the output of gate 10 is also 0 because of the inversion. The structure of FIG. 1B has a faster precharge time due to the parallel paths through which node W is precharged. This faster precharge time, however, comes at the cost of higher power dissipation during the evaluation phase, discussed next.
During the evaluation phase, the clock signal is at a logic 1 and the node W is conditionally discharged based upon the input signals and the logic function implemented by nMOS block 12. If node W becomes 0 during the evaluation phase, then the gate output becomes 1, otherwise remains at 0. This effect of switching from 0-to-1 is propagated serially as a Domino behavior, hence the name, when multiple Domino CMOS gates are cascaded to implement a logic function.
It should be noted that during the evaluation phase, the short circuit current is negligible in the structure of FIG. 1A, while the structure of FIG. 1B will dissipate current during the evaluation phase. To avoid this short-circuit current, sometimes the gate node of parallel pMOS 26 is connected to the output node as indicated by the dotted line. The problem with this is that it slows down the evaluation phase due to the increase loading at the output 24 of gate 10.
The unique behavior of the Domino logic gate significantly affects the ability to test the logic gate. The fact that the gate output is always 0 during precharge phase (clock 0) restricts the application of a test vector to the circuit. In a gate level model of the circuit, all of the nodes will be initialized to 0 during the precharge phase. Thus, conventional test vectors developed for static CMOS logic are not applicable. This affects both functional and scan testing of the Domino logic.
The fact that the gate output switch is unidirectionally (0-to-1) during evaluation phase also restricts the fault sensitization and fault-effect propagation. As a 0-to-1 transition is not obtained during the evaluation phase, maximum toggle coverage can only be 50%. It is worth noting that 1-to-0 transition is mandatory during precharge for all of the output nodes which are at logic 1 during evaluation phase. The effect of the transition, however, is not propagated due to initialization during precharge. Again, both functional and scan testing are affected.
Another attribute of Domino logic that impacts the testing of Domino logic circuits is the fact that the output is noninverting. This restricts the computation of test vectors as well as test application during both functional and scan testing. The dynamic behavior itself also imposes constraints on testing. Because in most realistic designs the Domino logic will be used in combination with static CMOS logic, which may be synchronized to a different clock, existing testing techniques are not applicable.
Accordingly, a need remains for the ability to test hybrid circuits built using Domino and static CMOS circuits.